ȸ»ç¼Ò°³
Çù·Â»ç
Terasic-FGPA Series
All FPGA Main Board
- Stratix III, IV, V
- Arria II. V
- Cyclone II, III, IV, V
- Bundle Solution
- USB Blaster
- max10
Daughter Card
- Interface conversion
- Video & Image
- Networking
- AD/DA
- Capsense
- Multimedia
- RF
SOC Platform
Microtronix-FPGA Series
IP Core
HSMC Daughter Card
Configurable Processor
FPGA Board
- HD Dev Solution
University Training Classes
Universities Classes using the DE2 Series
Altera ¿Â¶óÀÎ µ¥¸ð
Design Software
Embedded Processors
Licensing
Bundled Solutions
ARM Development Kit
ARM Development Kit
Single board computers
Computer-on-Module
AS ¼ö¸®
dimocore.com/terasicrepair
ÀÚ·á½Ç
°í°´¼¾ÅÍ
°øÁö»çÇ×
¹®ÀÇ°Ô½ÃÆÇ
 
 
Terasic-FGPA Series > FPGA Board > Cyclone V
   
Cyclone V GT FPGA Development Kit 
 
°¡    °Ý : °ßÀû¹®ÀÇ
Áß    ·® : 1,000g

 

The Altera¢ç Cyclone¢ç V GT FPGA Development Kit can be used to prototype Cyclone V GT FPGA or Cyclone V GX FPGA applications. It offers a quick and simple way to develop low-cost and low-power FPGA system-level designs and achieve rapid results. This kit supports a myriad of functionalities such as:

•FPGA prototyping
•FPGA power measurement
•Transceiver I/O performance up to 5.0 Gbps
•PCI Express¢ç (PCIe¢ç) Gen2 x4 (at 5.0 Gbps per lane)
•Endpoint or rootport support

 

FPGA Device

  • Configuration and Debug
  • Quad Serial Configuration device – EPCQ256 on FPGA
  • On-Board USB Blaster (Normal Type-B USB connector)
  • JTAG and AS mode configuration supported

Memory Device

  • Communication
  • Embedded USB-Blaster II (JTAG)
  • Fast Passive Parallel (PFL)
  • Altera EPCQ—EPCQ256SI16N (Quad Serial Configuration Device)

Standard communication ports

  • PCIe x4 edge connector
  • Gigabit Ethernet (GbE)
  • One SMA clock output
  • Two universal high-speed mezzanine card (HSMC) connectors, each with four high-speed serial transciever channels
  • One serial digital interface (SDI) channel —1 SMB for RX and 1 SMB for TX
  • Channel shared with HSMA via resistor stuffing option

Push buttons, DIP switches, and LEDs

Clocking

  • Programmable clock generator for FPGA reference clock input
  • 125 MHz LVDS oscillator for FPGA reference clock input
  • 148.5/148.35 MHz LVDS VCXO for FPGA reference clock input
  • 50 MHz single-ended oscillator for FPGA and MAX  V CPLD clock input
  • 100 MHz single-ended oscillator for MAX  V CPLD configuration clock input
  • SMA input (LVPECL)

Power

  • Laptop DC Input 14 – 20 V adapter
  • PCIe edge connector

System monitoring circuit

  • Power (Voltage, Current, Wattage)

Mechanical

  • PCIe card standard size (4.376" x 6.600")

Block Diagram

Documents

Title Version Size(KB) Date Added Download
Cyclone V GT FPGA Development Kit User Guide (PDF) -   2013-01-08
Cyclone V GT FPGA Development Board Reference Manual (PDF) -   2013-01-08

CD-ROM

Title Version Size(KB) Date Added Download
Kit installation -   2013-01-08

Please note that all the source codes are provided "as is". For further support or modification, please contactTerasic Support and your request will be transferred to Terasic Design Service.
More resources about IP and Dev. Kit are available on Altera User Forums.



 

 


»óÈ£¸í
: (ÁÖ)¿ì¸²Æ¼¾Ø¾ÆÀÌ   ´ëÇ¥ÀÚ¸í : ±è¼®¹ü   »ç¾÷ÀÚµî·Ï¹øÈ£ : 211-87-88913  À̸ÞÀÏ : jun@woorimtni.co.kr
º»»ç : ¼­¿ï °­³²±¸ ºÀÀº»ç·Î 129 °ÅÆòŸ¿î 1204È£ ´ëÇ¥ÀüÈ­ : 82-2-512-7661  Æѽº : 82-2-512-7662
Copyright(C) 2011 Woorimtni Technologies All Rights Reserved.